As is known in the art, transistors such as metal oxide silicon (MOS) transistors have been formed in isolated regions of a semiconductor body such as an epitaxial layer which is itself formed on a semiconductor, typically a bulk silicon substrate. With an n-channel MOS field effect transistor (FET), the body is of p-type conductivity and the source and drain regions are formed in the p-type conductivity body as N+ type conductivity regions. With a p-channel MOSFET, the body, or epitaxial layer, is of n-type conductivity and the source and drain regions are formed in the n-type conductivity body as P+ conductivity regions. It has been suggested that the semiconductor body, or layer, be formed on an insulating substrate or over an insulation layer formed in a semiconductor substrate. Such technology sometimes is referred to as silicon-on-insulator (SOI) technology. Silicon-on-insulator MOS technologies have a number of advantages over bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance; improved speed performance in higher-operating frequencies; reduced N+ to P+ spacing and hence higher packing density due to ease of isolation; and higher “soft error” upset immunity (i.e., immunity to the effects of alpha particle strikes).
Silicon-on-insulator technology is characterized by the formation of a thin silicon layer for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources and drains are formed by, for example, by implantation into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor (e.g., metal) layer structure. Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). However, the floating body can introduce dynamic instabilities in the operation of such a transistor.
Conventional SOI FET's have floating bodies in which the body or channel region of the FET is located on an insulator and not electrically connected to a fixed potential. These devices are known as partially depleted SOI devices and have the aforementioned advantages and disadvantages. Fully depleted SOI devices are those in which the layer of semiconductor is sufficiently thin, such that the entire thickness of the body regions is depleted of majority carriers when in the off state and both diffusions are at ground. Fully depleted devices offer additional advantages such as reduced short channel effect, increased transconductance and reduced threshold voltage sensitivity to changes and body doping. Furthermore, the kink effects and threshold voltage shifts caused by body charging in partially depleted devices are reduced.
One of the concerns with providing a fully depleted SOI MOSFET is the difficulty of in providing deep source/drain regions while at the same time maintaining the thickness of the body region sufficiently thin so that they are depleted of majority carriers when in the off state and both diffusions are at ground.